As device size shrinks down aggressively in advanced very large scale integration (VLSI) technology, increased process variation causes significant amounts of threshold voltage fluctuation. As the result, stability of static random access memory circuits (SRAMs) deteriorates due to the large threshold voltage mismatch between two neighboring transistors in a cell. The stability of the conventional 6-transistor (6-T) SRAM SRAM is dependent on the relative strengths of the various transistors in the cell. The transistors are typically optimized based on the expected device strengths to achieve the best power-performance characteristics, while maintaining the stability of the cell.
As shown in FIG. 1, the most-widely used, conventional (4-transistor (6-T) SRAM cell 100 has its worst stability during READ mode, i.e., when the word line 102 is asserted, with both the Bit-line 104 and Bit-line bar 106 being pre-charged high. In this condition, the voltage at the storage node which has a “0” logic value (node Q or 108) goes up during a READ cycle (with the access transistor 110 forming a resistive divider with the pull-down transistor 112. This is termed “read disturb noise”; if this increased voltage is larger than the trip voltage of the inverter (PL-NL pair formed by transistors 114, 116), the stored logic values will be flipped and data will be lost. The cell 100 also includes the right-hand inverter formed by PR-NR pair 118, 112, as well as the left-hand access device 120 and storage node 122 (Qb).
The read disturb noise problem can be alleviated by weakening the strength of the access transistor's 110, 120. However, the access transistors cannot be made arbitrarily small, since they are used to store the correct value to the cell during a WRITE operation. During the WRITE operation, as shown in FIG. 2, the word line 102 is asserted, with the data to be written (in this case a logical “1”) and its complementary value being asserted on the BL and BLb lines, 104, 106, respectively. If the cell 100 initially contained a value of “0” at node Qb, the access device on the right side 110 needs to overpower the pull-up PMOS device 118 to write the correct value to the cell 100, and hence needs to be a strong device. Thus, there exist conflicting requirements for the strength of the access transistor 110.